As data rates continue to increase, signal integrity issues have become the most critical factor for design engineers to consider. This exponential rise in data rates can be seen in applications such as handheld mobile devices and consumer display products, high bandwidth routers/switches, and so on. Jitter (noise) is the number one cause of degrading signal integrity in designs. In addition to using layouts, impedance matching, and more expensive materials to implement signal integrity enhancement techniques, designers can simply add a jitter eliminator such as an equalizer to the design to solve the jitter problem. In this way, designers do not need to focus on signal integrity issues, but instead focus on the core design of the system.

　　 Signal routing has traditionally been considered as a simple concept. From the perspective of wiring, there is no difference between video signals, speech signals, or data signals. Therefore, in the past, few people were concerned about signal wiring. However, the situation has now completely changed. Video signal transmission speed has reached 3.3Gbps per channel, and the data signal is far more than 5Gbps per channel. High-speed serial standards such as PCI Express, XAUI, SATA, TMDS, and DisplayPort require design teams and engineers not only to consider signal integrity issues, but also to have a deep understanding of how it will affect system performance and reliability. . 

　　 In order to master this knowledge, engineers must first understand what factors affect the integrity of the signal in the system. The signal integrity loss in the system can be observed by adding signal jitter. The total jitter of the system consists of two types of jitter, namely random jitter and deterministic jitter. Random jitter is infinite and essentially obeys Gaussian distribution, while deterministic jitter is limited and predictable. In 90% of systems, deterministic jitter is a major signal integrity problem that design engineers must address. 

　　 Deterministic jitter includes intersymbol interference (ISI), duty cycle distortion, and periodic jitter, which are caused by bandwidth limitations, clock cycle asymmetry, and cross-coupling or EMI problems, respectively. Passive devices such as connectors, PCB traces, long cables, and other passive devices routed along the traces are the main sources of deterministic jitter.

　　 The higher the signal frequency, the greater the attenuation, and therefore the power level mismatch in the specified data stream, which in turn causes the ISI to occur in the signal. The ISI will reduce signal integrity, which is enough to prevent the receiver from correctly extracting any real data from the signal at the receiving end. 

   The reason for the power level mismatch is that no design engineer can guarantee the transmission of data in the design. The data may be constantly changing (0-10-10-1-0-1, etc.), or it may be constant (1-1-1-1-1-1, etc.). Obviously, the duty cycle of the above 6 change bits is 6 times smaller than the duty cycle of the 6 "1" constant data streams. Since the duty cycle is 6 times smaller, the signal frequency is 6 times higher. If the data stream contains both types, the receiver signal will have a very different power level because the higher the frequency, the greater the attenuation. 

Resolving power mismatch problems 

    The standard for most high-speed signals is to minimize the number of consecutive bits that do not change, such as 8B/10B encoding. This encoding scheme ensures that the data stream will not have more than 4 consecutive bits. However, there is still the possibility of a 4 times higher power part in the receiver signal. 

    To compensate for power level mismatches to reduce ISI, designers can use equalization or de-emphasis techniques. The equalization technique will power up all high-speed bits so that the high-speed bits and the low-speed bits in the received signal have the same power level, thereby reducing power level mismatch. 

     The opposite is true for de-emphasis and equalization, but with the same goal: Minimize power level mismatch. It is done by lowering the power of low-bit bits, while equalization is increasing the power of high-speed bits. Therefore, de-emphasis can only act on the transmitted bits, and equalization can only act on the received bits. 

   This is not the only way to eliminate deterministic jitter, but users are most likely to require some type of transmitter jitter eliminator, such as de-emphasis described above. The true jitter cancellation scheme requires both of these circuits. 

    Don't let jitter degrade your design because low-cost signal conditioning solutions are already on the market. Equilibrium and de-emphasis circuits eliminate jitter due to long FR traces, connectors, and long cables, and you don't have to worry about understanding the details of the signal integrity enhancement techniques. Let the jitter terminator do the trick!